Intel Pentium Pro Family, Developer'S Manual, Page: 298 / 328

A-8
SIGNALS REFERENCE
A.1.15. BPRI# (I)
The BPRI# signal is the Priority-agent Bus Request signal. The priority agent arbitrates for the
bus by asserting BPRI#. The priority agent is always be the next bus owner. Observing BPRI#
active causes the current symmetric owner to stop issuing new requests, unless such requests are
part of an ongoing locked operation.
If LOCK# is sampled inactive two clocks from BPRI# driven asserted, the priority agent can is-
sue a new request within four clocks of asserting BPRI#. The priority agent can further reduce
its arbitration latency to two clocks if it samples active ADS# and inactive LOCK# on the clock
in which BPRI# was driven active and to three clocks if it samples active ADS# and inactive
LOCK# on the clock in which BPRI# was sampled active. If LOCK# is sampled active, the pri-
ority agent must wait for LOCK# deasserted and gains bus ownership in two clocks after
LOCK# is sampled deasserted. The priority agent can keep BPRI# asserted until all of its re-
quests are completed and can release the bus by de-asserting BPRI# as early as the same clock
edge on which it issues the last request.
On observation of active AERR#, RESET#, or BINIT#, BPRI# must be deasserted in the next
clock. BPRI# can be reasserted in the clock after sampling the RESET# active-to-inactive tran-
sition or three clocks after sampling BINIT# active and RESET# inactive. On AERR# assertion,
if the priority agent is in the middle of a bus-locked operation, BPRI# must be re-asserted after
two clocks, otherwise BPRI# must stay inactive for at least 4 clocks.
After the RESET# inactive transition, Pentium Pro processor bus agents begin BPRI# and BNR#
sampling on BNR# sample points. When both BNR# and BPRI# are observed inactive on a
BNR# sampling point, the APIC units in Pentium Pro processors on a common APIC bus are
synchronized. In a system with multiple Pentium Pro processor bus clusters sharing a common
APIC bus, BPRI# signals of all clusters must be asserted after RESET# until BNR# is observed
inactive on a BNR# sampling point. The BPRI# signal on all Pentium Pro processor buses must
then be deasserted within 100ns of each other to accomplish APIC bus synchronization across
all processors.
A.1.16. BR0#(I/O), BR[3:1]# (I)
The BR[3:0]# pins are the physical bus request pins that drive the BREQ[3:0]# signals in the
system. The BREQ[3:0]# signals are interconnected in a rotating manner to individual processor
pins. #. Table A-4 gives the rotating interconnect between the processor and bus signals.
Table A-4. BR0#(I/O), BR1#, BR2#, BR3# Signals Rotating Interconnect
Bus Signal Agent 0 Pins Agent 1 Pins Agent 2 Pins Agent 3 Pins
BREQ0# BR0# BR3# BR2# BR1#
BREQ1# BR1# BR0# BR3# BR2#
BREQ2# BR2# BR1# BR0# BR3#
BREQ3# BR3# BR2# BR1# BR0#