Intel Pentium Pro Family, Developer'S Manual, Page: 313 / 328

A-23
SIGNALS REFERENCE
A.1.55. TRDY# (I)
The TRDY# signal is the target Ready signal. It is asserted by the target in the Response Phase
to indicate that the target is ready to receive write or implicit writeback data transfer. This en-
ables the request initiator or the snooping agent to begin the appropriate data transfer. There will
be no data transfer after a TRDY# assertion if a write has zero length indicated in the Request
Phase. The data transfer is optional if an implicit writeback occurs for a transaction which writes
a full cache line (the Pentium Pro processor will perform the implicit writeback).
TRDY# for a write transaction is driven by the addressed agent when:
•
when the transaction has a write or writeback data transfer
•
it has a free buffer available to receive the write data
•
a minimum of 3 clocks after ADS# for the transaction
•
the transaction reaches the top-of-the-In-order Queue
•
a minimum of 1 clock after RS[2:0]# active assertion for transaction “n-1”.
(After the transaction reaches the top of the In-order Queue).
TRDY# for an implicit writeback is driven by the addressed agent when:
•
transaction has an implicit writeback data transfer indicated in the Snoop Result Phase.
•
it has a free cache line buffer to receive the cache line writeback
•
if the transaction also has a request initiated transfer, that the request initiated TRDY# was
asserted and then deasserted (TRDY# must be deasserted for at least one clock between the
TRDY# for the write and the TRDY# for the implicit writeback),
•
a minimum of 1 clock after RS[2:0]# active assertion for transaction “n-1”.
(After the transaction reaches the top of the In-order Queue).
TRDY# for a write or an implicit writeback may be deasserted when:
•
inactive DBSY# and active TRDY# are observed.
•
DBSY# is observed inactive on the clock TRDY# is asserted.
•
a minimum of three clocks can be guaranteed between two active-to-inactive transitions of
TRDY#
•
the response is driven on RS[2:0]#.
•
inactive DBSY# and active TRDY# are observed for a write, and TRDY# is required for an
implicit writeback.
A.1.56. TRST# (I)
The TRST# signal is an additional System Support group JTAG-support signal.