Intel Pentium Pro Family, Developer'S Manual, Page: 300 / 328

A-10
SIGNALS REFERENCE
A.1.18. D[63:0]# (I/O)
The D[63:0]# signals are the data signals. They are driven during the Data Phase by the agent
responsible for driving the data. These signals provide a 64-bit data path between various Pen-
tium Pro processor bus agents. 32-byte line transfers require four data transfer clocks with valid
data on all eight bytes. Partial transfers require one data transfer clock with valid data on the
byte(s) indicated by active byte enables BE[7:0]#. Data signals not valid for a particular transfer
must still have correct ECC (if data bus ECC is selected). If BE0# is asserted, D[7:0]# transfers
the least significant byte. If BE7# is asserted, D[63:56]# transfers the most significant byte.
The data driver asserts DRDY# to indicate a valid data transfer. If the Data Phase involves more
than one clock the data driver also asserts DBSY# at the beginning of the Data Phase and de-
asserts DBSY# no earlier than on the same clock that it performs the last data transfer.
A.1.19. DBSY# (I/O)
The DBSY# signal is the Data-bus Busy signal. It indicates that the data bus is busy. It is asserted
by the agent responsible for driving the data during the Data Phase, provided the Data Phase in-
volves more than one clock. DBSY# is asserted at the beginning of the Data Phase and may be
deasserted on or after the clock on which the last data is driven. The data bus is released one
clock after DBSY# is deasserted.
When normal read data is being returned, the Data Phase begins with the Response Phase. Thus
the agent returning read data can assert DBSY# when the transaction reaches the top of the In-
order Queue and it is ready to return response on RS[2:0]# signals. In response to a write request,
the agent driving the write data must drive DBSY# active after the write transaction reaches the
top of the In-order Queue and it sees active TRDY# with inactive DBSY# indicating that the tar-
get is ready to receive data. For an implicit writeback response, the snoop agent must assert
DBSY# active after the target memory agent of the implicit writeback asserts TRDY#. Implicit
writeback TRDY# assertion begins after the transaction reaches the top of the In-order Queue,
and TRDY# de-assertion associated with the write portion of the transaction, if any is completed.
In this case, the memory agent guarantees assertion of implicit writeback response in the same
clock in which the snooping agent asserts DBSY#.
A.1.20. DEFER# (I)
The DEFER# signal is the defer signal. It is asserted by an agent during the Snoop Phase to in-
dicate that the transaction cannot be guaranteed in-order completion. Assertion of DEFER# is
normally the responsibility of the addressed memory agent or I/O agent. For systems that involve
resources on a system bus other than the Pentium Pro processor bus, a bridge agent can accept
the DEFER# assertion responsibility on behalf of the addressed agent.
When HITM# and DEFER# are both active during the Snoop Phase, HITM# is given priority
and the transaction must be completed with implicit writeback response. If HITM# is inactive,
and DEFER# active, the agent asserting DEFER# must complete the transaction with a Deferred
or Retry response.