Intel Pentium Pro Family, Developer'S Manual, Page: 38 / 328

3-2
BUS OVERVIEW
When signal values are referenced in tables, a 0 indicates inactive and a 1 indicates active. 0 and
1 do not reflect voltage levels. Remember, a # after a signal name indicates active low. An entry
of 1 for ADS# means that ADS# is active, with a low voltage level.
3.2. SIGNALING ON THE PENTIUM
®
PRO PROCESSOR BUS
The Pentium Pro processor bus supports a synchronous latched protocol. On the rising edge of
the bus clock, all agents on the Pentium Pro processor bus are required to drive their active out-
puts and sample required inputs. No additional logic is located in the output and input paths be-
tween the buffer and the latch stage, thus keeping setup and hold times constant for all bus
signals following the latched protocol. The Pentium Pro processor bus requires that every input
be sampled during a valid sampling window on a rising clock edge and its effect be driven
out no sooner than the next rising clock edge. This approach allows one full clock for inter-
component communication and at least one full clock at the receiver to compute a response.
Figure 3-1 illustrates the latched bus protocol as it appears on the bus. In subsequent descrip-
tions, the protocol is described as “B# is asserted in the clock after A# is observed active”, or
“B# is asserted two clocks after A# is asserted”. Note that A# is asserted in T1, but not observed
active until T2. The receiving agent uses T2 to determine its response and asserts B# in T3. Oth-
er agents observe B# active in T4.
The square and circle symbols are used in the timing diagrams to indicate the clock in which
particular signals of interest are driven and sampled. The square indicates that a signal is driven
(asserted, initiated) in that clock. The circle indicates that a signal is sampled (observed, latched)
in that clock.