Intel Pentium Pro Family, Developer'S Manual, Page: 124 / 328

5-19
BUS TRANSACTIONS AND OPERATIONS
Before T9, the addressed response agent obtains the data required in the original request. In T9,
the original response agent issues a Deferred Reply Transaction, using the value latched from
the DID[7:0]# signals in the original transaction as the address. In T13, the response agent drives
a valid level on the HIT# signal to indicate the final cache state of the returned line. The original
requestor picks up snoop responsibility. In T15, it drives normal completion response and also
begins the Data Phase.
In T10, the original requesting agent observes the Deferred Reply Transaction. It matches the
DID[7:0]# to the Deferred ID stored with the original request in its outstanding transaction
queue. The original requesting agent observes the final state of the returned cache line in T14.
In T16, it observes the transaction response and removes the transaction from the outstanding
transaction queue and the In-order Queue. This completes the entire deferred operation
sequence.
5.3.4. Locked Operations
Locked operations provide a means of synchronization in a multiprocessor environment. They
guarantee indivisible sequencing between multiple memory transactions.
A locked instruction is guaranteed to lock the area of memory defined by the destination oper-
and. In addition, a lock’s integrity is not affected by the memory operand’s alignment.
In previous generation processors, lock semantics were implemented with a [split] bus lock. This
approach, although sufficient to guarantee indivisibility, is not always necessary or efficient in a
writeback caching agent. During bus lock, other agents are prevented from issuing bus transac-
tions. In multiprocessing systems, it is desirable to reduce the data bus bandwidth demands of
locked operations, so the Pentium Pro processor implements cache locks. Cache locks allow
locked operations to take place in the cache without tying up the bus.
A locked operation in the Intel386 and Intel486 architecture involves an indivisible read-
modify-write operation on the lock variable. Based on the memory type and alignment of the
lock variable, a locked operation is carried out using one of three options:
Cache Lock. When the lock variable is in a writeback-cacheable (WB) memory range and the
lock variable is contained in one cache line, the locked operation can be executed by:
1) executing any bus transactions necessary to bring the line into the Exclusive or Modified
cache state, and 2) executing the locked read-modify-write sequence in the cache, placing the
line in the Modified state.
[Split] Bus Lock. When the lock variable cannot use a cache lock (due to attribute conflicts) or
crosses an 8-byte boundary, the locked operation is issued on the Pentium Pro processor bus. The
bus is locked during the entire read-modify-write sequence to guarantee indivisibility.
Some implementations might use a bus lock or split lock even when a cache lock is allowed.