3-4
BUS OVERVIEW
3.3.
PENTIUM
®
PRO PROCESSOR BUS PROTOCOL OVERVIEW
Bus activity is hierarchically organized into operations, transactions, and phases.
An operation is a bus procedure that appears atomic to software even though it may not be atom-
ic on the bus. An operation may consist of a single bus transaction, but sometimes may involve
multiple bus transactions or a single transaction with multiple data transfers. Examples of com-
plex bus operations include: locked read/modify/write operations and deferred operations.
A transaction is the set of bus activities related to a single bus request. A transaction begins with
bus arbitration, and the assertion of ADS# and a transaction address. Transactions are driven to
transfer data, to inquire about or change cache state, or to provide the system with information.
A transaction contains up to six phases. A phase uses a specific set of signals to communicate a
particular type of information. The six phases of the Pentium Pro processor bus protocol are:
•
Arbitration
•
Request
•
Error
•
Snoop
•
Response
•
Data
Not all transactions contain all phases, and some phases can be overlapped.
3.3.1.
Transaction Phase Description
Figure 3-2 shows all of the Pentium Pro processor bus transaction phases for two transactions
with data transfers.
Summary of Contents for Pentium Pro Family
Page 17: ...1 Component Introduction ...
Page 26: ...2 Pentium Pro Processor Architecture Overview ...
Page 27: ......
Page 36: ...3 Bus Overview ...
Page 62: ...4 Bus Protocol ...
Page 105: ...5 Bus Transactions and Operations ...
Page 126: ...6 Range Registers ...
Page 131: ...7 Cache Protocol ...
Page 135: ...8 Data Integrity ...
Page 148: ...9 Configuration ...
Page 161: ...10 Pentium Pro Processor Test Access Port TAP ...
Page 172: ...11 Electrical Specifications ...
Page 201: ...12 GTL Interface Specification ...
Page 229: ...13 3 3V Tolerant Signal Quality Specifications ...
Page 233: ...14 Thermal Specifications ...
Page 239: ...15 Mechanical Specifications ...
Page 241: ...15 2 MECHANICAL SPECIFICATIONS s Figure 15 1 Package Dimensions Bottom View ...
Page 252: ...16 Tools ...
Page 260: ...16 8 TOOLS Figure 16 4 Generic MP System Layout for Debug Port Connection ...
Page 264: ...17 OverDrive Processor Socket Specification ...
Page 290: ...A Signals Reference ...
Page 320: ...Index ...
Page 328: ......