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5-3
BUS TRANSACTIONS AND OPERATIONS
Ab[15:3]# are used to encode additional information about the transaction as follows:
The ASZ[1:0]# signals are used to support agents with different memory addressing capability
to coexist on the same bus. The bits indicate what address range is being addressed as shown in
the table below. If a reserved range is indicated, then Snooping Agents and Responding agents
must ignore this transaction.
The remaining three bits in the REQa[2:0]# field support identification of different types of
memory transactions.
The LEN[1:0]# signals are used to indicate the length of the memory transaction. It indicates
how much data will be transferred over the bus. The Pentium Pro processor will issue 0 - 8 byte
and 32 byte memory transactions. Response to reserved encodings should be the largest transfer
size supported.
BE[7:0]# is used in conjunction with LEN[1:0]#. If 8 bytes or more are to be transferred, then
BE[7:0]# indicates that all bytes are enabled. If less than 8 bytes are to be transferred, then
BE[7:0]# indicates which bytes. Transaction lengths of less than 8 bytes may have any combi-
nation of byte enables. If no bytes are enabled, then no data is transferred (in the absence of an
Implicit Writeback). A zero byte-count transfer is indicated by BE[7:0]# = 00000000B and an
eight or more byte transfer is indicated by BE[7:0]# = 11111111B
Zero length requests (LEN= 00B and BE = 00H) for read transactions are modeled after the
Memory (Read) Invalidate transaction. Response must be No Data Response in the absence of
HITM# or DEFER# assertion.
Ab[15:8]#
Ab[7:3]#
BE[7:0]#
SMMEM#
SPLCK#
rsvd
DEN#
rsvd
ASZ[1:0]#
Address Range
Observing Agents
0
0
0 <= A[35:3]# < 4 GB
32 & 36 bit agents
0
1
4 GB <= A[35:3]# < 64 GB
36 bit agents
1
x
Reserved
None
LEN[1:0]#
Transaction Length
0
0
0 - 8 bytes
0
1
16 bytes
1
0
32 bytes
1
1
Reserved
Summary of Contents for Pentium Pro Family
Page 17: ...1 Component Introduction ...
Page 26: ...2 Pentium Pro Processor Architecture Overview ...
Page 27: ......
Page 36: ...3 Bus Overview ...
Page 62: ...4 Bus Protocol ...
Page 105: ...5 Bus Transactions and Operations ...
Page 126: ...6 Range Registers ...
Page 131: ...7 Cache Protocol ...
Page 135: ...8 Data Integrity ...
Page 148: ...9 Configuration ...
Page 161: ...10 Pentium Pro Processor Test Access Port TAP ...
Page 172: ...11 Electrical Specifications ...
Page 201: ...12 GTL Interface Specification ...
Page 229: ...13 3 3V Tolerant Signal Quality Specifications ...
Page 233: ...14 Thermal Specifications ...
Page 239: ...15 Mechanical Specifications ...
Page 241: ...15 2 MECHANICAL SPECIFICATIONS s Figure 15 1 Package Dimensions Bottom View ...
Page 252: ...16 Tools ...
Page 260: ...16 8 TOOLS Figure 16 4 Generic MP System Layout for Debug Port Connection ...
Page 264: ...17 OverDrive Processor Socket Specification ...
Page 290: ...A Signals Reference ...
Page 320: ...Index ...
Page 328: ......