HP 64783A, User Manual

Page: 372 / 816

the traced data rate is "Fast". It cannot perform counts of time between the traced
states.
Choosing "Very Fast" specifies that the burst data rate of the traced activity is
greater than 20.00 MHz. The 1K analyzer cannot perform any counts when the
traced data rate is " Very Fast".
If burst cycles are not being used, set the "Analyzer Speed" to "Slow".
The MC68040 analyzer clock is set to "Very Fast" by default. The 1K analyzer can
capture all types of bus cycles correctly up to the maximum clock rate of 40 MHz,
but cannot correctly count states or time at higher speeds for certain bus cycle types.
The worst-case situation is one where a zero-wait state burst cycle is performed.
The analyzer clock rate for burst cycles is given by the equation:
Analyzer Clock Rate
=
Processor Clock Rate
(
BCLK
)
(
1
+
number of wait states
)
To determine the correct selection, calculate the maximum data rate by using the
above equation. Remember that the emulator requires one wait state for all accesses
when the external clock is greater than or equal to 25 MHz. Then choose the data
rate option according to the data rate.
If no burst cycles are performed, the 1K analyzer clock speed can be set "Slow".
Chapter 8: Configuring the Emulator
Setting the Trace Options
342