HP 64783A, User Manual

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To map memory ranges in which data is not
loaded into the caches
•
Choose "Yes" or "No" for the "Transfer Cache Inhibit" configuration option in the
"Modify Map Entry" or "Add New Entry" dialog box.
Choosing "Yes" specifies that no data will be loaded into either the instruction
cache or data cache during any transactions occuring in the associated memory
range. This choice is useful when you need to have all transactions appear on the
external buses to allow the emulation-bus analyzer to capture complete traces of
processor activity.
Choosing "No" specifies that data will be loaded into either the instruction cache or
data cache, as applicable, during transactions occurring in the associated memory
range. This choice is useful when you need to have transactions completed in the
fastest and most efficient manner. Use of processor caches increases the processor
speed of execution.
To map memory in which the emulator will
terminate bus cycles
•
Choose "Yes" or "No" for the "Emulator Terminates Bus Cycles" configuration
option in the "Modify Map Entry" or "Add New Entry" dialog box.
Choosing "Yes" causes the emulator to terminate bus cycles without regard to the
state of the target system. This is useful in ranges where the TA or TEA or both
signals from the target system are not available. The danger of including this
option is that the emulator may become out of sync with the target system if the
target system provides these signals.
Choosing "No" ensures that the timing of cycle termination signals will not cause
the emulator and target system to become out of sync. No emulation bus cycle will
be terminated until the TA or TEA signal is received from the target system.
Chapter 8: Configuring the Emulator
Mapping Memory
328