Main Memory System
Overview
The main memory system is implemented in the NVAX memory
controller chip (NMC). The NMC communicates with SIM modules
over the NVAX memory interconnect (NMI). Up to eight SIM
modules are supported, for a maximum of 128 MB of main
memory.
The NMC serves as an interface between the NDAL and NVAX
memory interconnect. The NMI is comprised of the set of signals
leading from the NMC to the memory modules, and provides a
64-bit path to the memory modules. The arbiter for the NDAL is
also built into the NMC.
NVAX Memory
Subsystem
The NMC controls and passes data to or from, one or two sets
of SIM modules using a bank interleaved memory access. It
responds to commands from the CPU and the I/O adapter (NCA).
The NMC is never a commander on the NDAL.
Each set of memory modules can have either zero or four SIM
modules. The memory modules can be either 4 MB (1-MB
DRAMs) or 16 MB (4-MB DRAMs). The SIM modules in each
set must be homogenous (no mixing of 4-MB and 16-MB SIM
modules within a set) although the types of SIM modules can
differ between the two sets (for example, a set of 4-MB SIM
modules and a set of 16-MB SIM modules). The minimum
configuration is 16 MB. Each SIM module consists of fast page
mode 100 ns RAS access time DRAMs.
1–24
