Central Processor Unit,
Continued
cache memory, as well as providing a secure interlock mechanism
for synchronization between NVAX and the I/O devices.
The memory controller is implemented by the NVAX memory
controller chip (DC244). The NMC is an ECC protected memory
controller. The NMC controls transactions between the main
memory and the NVAX, and between main memory and any of
the I/O devices (through the NCA interface). In addition, the
NMC has a key role in maintaining main memory coherency with
the NVAX Pcache and Bcache through the use of ownership bits.
The NMC interfaces the NVAX and I/O subsystem to up to 128
MB of main memory. Main memory is comprised of one or two
sets of SIM modules. Each set contains either four 4-MB SIM
modules or four 16-MB SIM modules. The NMC controls access to
shared memory locations through the use of the ownership bits,
thereby providing a reliable interlock mechanism for memory that
is shared between the NVAX and the I/O devices.
NVAX
Data/Address
Lines
In order to maximize the bandwidth of the bus connecting the
CPU to the memory and I/O controllers, the NVAX chip set
(NVAX, NMC, NCA) communicates over a "pended" bus called the
NDAL. The main feature of this bus is that devices requesting
read data do not tie up the bus while waiting for the return data.
Rather, a device issues one of the "read" commands on the NDAL
and then relinquishes control of the bus to other devices. This is
so other transactions can be performed while the responder to the
first device prepares to send back the data associated with the
read request. Because of the pended nature of the bus, the NDAL
bus command set includes separate transactions for returning
data from an earlier read cycle.
Processor
State
The processor state consists of that portion of the state of a
process that is stored in processor registers rather than in
memory. The processor state is composed of 16 general purpose
registers (GPRs), the processor status longword (PSL), and the
internal processor registers (IPRs).
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