Cache Memory,
Continued
layer for storing references. Furthermore, care must be taken to
ensure that the state of the system is singularly and accurately
represented by the combined contents of the caches and main
memory.
In the KA49 this issue is most critical between main memory and
the Bcache and Pcache, because main memory can be accessed
by DMA devices as well as the NVAX CPU. Furthermore, this
problem is complicated by the writeback nature of the Bcache.
This write-back mechanism, while significantly decreasing
the latency of write operations, complicates the problem of
maintaining a coherent and consistent representation of main
memory in the face of DMA traffic.
Cached
References
Any reference that can be stored by the VIC, the Pcache, or the
Bcache is called a cached reference. The Pcache and Bcache store
CPU read references to the VAX memory space (bit <29> of the
physical address = 0) only. They do not store references to the
VAX I/O space.
Whenever the CPU generates a non-cached reference, or a cached
reference not stored in any of the three caches, a single hexaword
reference of the same type is generated on the NDAL Bus.
Whenever the CPU generates a cached reference that is stored in
one of the caches, no reference is generated on the NDAL Bus.
Virtual
Instruction
Cache
Before any instruction can be executed, it must first be fetched
from memory. The NVAX CPU contains an instruction prefetcher
that fetches sequential instructions ahead of the instruction
currently being executed. This is done in an attempt to reduce
the effective access time of the instruction fetch by pipelining it
with decode and instruction execution. The instruction prefetcher
maintains an instruction prefetch queue (IPQ) of up to 16 bytes
(4 longwords) of I-stream data. In order to fill the IPQ, the
prefetcher sends I-stream read requests to the Virtual Instruction
Cache (VIC).
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