Central Processor Unit,
Continued
Central
Processing
Subsystem
The NVAX CPU (DC246) chip is the heart of the KA49 CPU
module. It executes the VAX base instruction group as defined
in the VAX Architecture Reference Manual plus the optional VAX
vector instructions and the virtual machine instructions. The
NVAX processor also supports full VAX memory management with
demand paging and a 4-gigabyte virtual address space.
Three Level
Cache
Architecture
The KA49 CPU module uses a three-level cache architecture to
maximize performance. The first level of cache, referred to as
the virtual instruction cache (VIC), is 2 KB in size, and is located
on the CPU chip. This cache handles instructions only (no data
references), and deals only with virtual addresses. In this way
the CPU can obtain instruction information without the need for
virtual to physical address translation, thereby decreasing latency
and improving performance.
The second level of cache, referred to as the primary cache
(Pcache), is 8 KB in size and is located on the CPU chip. This
cache implements a write-through instruction and data cache, and
helps to reduce latency on access to data and instructions that are
not found in the VIC. The Pcache uses physical addresses.
The third level of cache, referred to as the backup write cache
(Bcache) is 256 KB. The Bcache is controlled by the Bcache
controller located in the CPU chip. The data and tag store
memory for this cache is located in SRAM chips on the KA49
CPU module. The Bcache uses physical addresses.
Graphics
Subsystem
The graphics subsystem consists of either the LCSPX for low cost
graphics support or the SPXg/gt modules, which support high
performance graphics. Two connectors are provided on the module
that provide a unique interface to each.
Continued on next page
1–7
