Cache Memory,
Continued
The VIC is a 2-KB, direct-mapped cache for caching I-stream
data. The VIC is located within the NVAX CPU chip. In order to
reduce the overhead associated with virtual-to-physical address
translation, the VIC caches references based on virtual addresses.
In the event that the virtual references made by the instruction
prefetcher hit in the VIC, the I-stream data is loaded from the
VIC directly to the IPQ.
If the references made by the instruction prefetcher miss in the
VIC, then the VIC issues an I-stream read request on behalf of
the instruction prefetcher to the next level of memory hierarchy,
the Pcache.
Primary Cache
The primary cache (Pcache) is a two-way set associative, read
allocate, no-write allocate, write through, physical address cache
of I-stream and D-stream data. It stores 8192 bytes (8K) of data
and 256 tags corresponding to 256 hexaword blocks (1 hexaword =
32 bytes). Each tag is 20 bits wide corresponding to bits <31:12>
of the physical address.
There are four quadword subblocks per block with a valid bit
associated with each subblock. The access size for both Pcache
reads and writes is one quadword. Byte parity is maintained
for each byte of data (32 bits per block). One bit of parity is
maintained for every tag. The Pcache has a one cycle access and
a one cycle repetition rate for both reads and writes.
The Pcache represents the first level of D-stream memory
hierarchy and the second level of I-stream memory hierarchy in
all NVAX computer systems. Pcache entries must be invalidated
in order to maintain cache coherency with higher levels of the
memory hierarchy.
The Pcache is located within the NVAX CPU chip. Unlike the
VIC, the Pcache is based on physical addresses rather than
virtual addresses. The Pcache handles I-stream requests from
the VIC, as well as D-stream requests for instruction operands.
The Pcache uses a write-through scheme for handling writes to
memory locations which are contained in the Pcache. In this
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