List of Figures
ARM DDI 0301H
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Figure 11-1
Core and coprocessor pipelines ............................................................................................... 11-5
Figure 11-2
Coprocessor pipeline and queues ............................................................................................ 11-5
Figure 11-3
Coprocessor pipeline ................................................................................................................ 11-6
Figure 11-4
Token queue buffers ................................................................................................................. 11-9
Figure 11-5
Queue reading and writing ...................................................................................................... 11-10
Figure 11-6
Queue flushing ........................................................................................................................ 11-11
Figure 11-7
Instruction queue .................................................................................................................... 11-12
Figure 11-8
Coprocessor data transfer ...................................................................................................... 11-15
Figure 11-9
Instruction iteration for loads ................................................................................................... 11-16
Figure 11-10
Load data buffering ................................................................................................................. 11-17
Figure 12-1
Connection of a VIC to the processor ....................................................................................... 12-3
Figure 12-2
VIC port timing example ............................................................................................................ 12-5
Figure 12-3
Interrupt entry sequence ........................................................................................................... 12-7
Figure 13-1
Typical debug system ............................................................................................................... 13-2
Figure 13-2
Debug ID Register format ......................................................................................................... 13-6
Figure 13-3
Debug Status and Control Register format ............................................................................... 13-8
Figure 13-4
DTR format ............................................................................................................................. 13-12
Figure 13-5
Vector Catch Register format .................................................................................................. 13-13
Figure 13-6
Breakpoint Control Registers, format ...................................................................................... 13-17
Figure 13-7
Watchpoint Control Registers, format ..................................................................................... 13-21
Figure 14-1
JTAG DBGTAP state machine diagram .................................................................................... 14-2
Figure 14-2
RealView ICE clock synchronization ......................................................................................... 14-3
Figure 14-3
Bypass register bit order ........................................................................................................... 14-8
Figure 14-4
Device ID code register bit order .............................................................................................. 14-9
Figure 14-5
Instruction register bit order ...................................................................................................... 14-9
Figure 14-6
Scan chain select register bit order ......................................................................................... 14-10
Figure 14-7
Scan chain 0 bit order ............................................................................................................. 14-11
Figure 14-8
Scan chain 1 bit order ............................................................................................................. 14-11
Figure 14-9
Scan chain 4 bit order ............................................................................................................. 14-13
Figure 14-10
Scan chain 5 bit order, EXTEST selected ............................................................................... 14-15
Figure 14-11
Scan chain 5 bit order, INTEST selected ................................................................................ 14-15
Figure 14-12
Scan chain 6 bit order ............................................................................................................. 14-17
Figure 14-13
Scan chain 7 bit order ............................................................................................................. 14-18
Figure 14-14
Behavior of the ITRsel IR instruction ...................................................................................... 14-22
Figure 15-1
ETMCPADDRESS format ......................................................................................................... 15-7
Figure 18-1
FMAC pipeline .......................................................................................................................... 18-6
Figure 18-2
DS pipeline ................................................................................................................................ 18-8
Figure 18-3
LS pipeline ................................................................................................................................ 18-9
Figure 19-1
Single-precision data format ..................................................................................................... 19-3
Figure 19-2
Double-precision data format .................................................................................................... 19-4
Figure 19-3
Register file access ................................................................................................................... 19-5
Figure 19-4
Register banks ........................................................................................................................ 19-10
Figure 20-1
FMDRR instruction format ........................................................................................................ 20-8
Figure 20-2
FMRRD instruction format ........................................................................................................ 20-9
Figure 20-3
FMSRR instruction format ....................................................................................................... 20-10
Figure 20-4
FMRRS instruction format ....................................................................................................... 20-11
Figure 20-5
Floating-Point System ID Register .......................................................................................... 20-13
Figure 20-6
Floating-Point Status and Control Register ............................................................................. 20-14
Figure 20-7
Floating-Point Exception Register ........................................................................................... 20-17
Figure 20-8
Media and VFP Feature Register 0 format ............................................................................. 20-19
Figure 20-9
Media and VFP Feature Register 1 format ............................................................................. 20-20