Anritsu MX183000A, Operation Manual, Page: 68 / 226

Chapter 4 Operation
4-14
Table 4.4.2-1 PCIe Link Sequence Setup Items
Item Description
Specification Selects the PCIe specification from Rev1.0/1.1 (2.5 GT/s),
2.0 (5.0 GT/s), 3.0/3.1 (8.0 GT/s), and 4.0 (16.0 GT/s).
If MU181000A/B is installed, set the 32G PPG Operation
Bitrate to Rev1:2.5 Gbit/s, Rev2:5.0 Gbit/s, Rev3:8.0
Gbit/s, and Rev4:16 Gbit/s respectively.
Altering this item changes the link training sequence
displayed in Sequence Editor.
Loopback through Sets the sequence type for looping back DUT. Altering
this item changes the link training sequence displayed in
Sequence Editor.
The following selections are available depending on the
Specification Rev. setting.
Revision Configuration Recovery
1.0/1.1(2.5 GT/s)

2.0(5.0 GT/s)
 
3.0/3.1(8.0 GT/s)
 
4.0(16.0 GT/s)

Test Pattern Selects the test pattern output repeatedly from
Compliance or PRBS after completing the link training
sequence transmission.
Selecting Compliance displays the PCIe standard test
pattern selection controller, and selecting PRBS displays
the PRBS level setting controller.
The pattern is set automatically in accordance with 32G
PPG/ED to suit the Compliance/PRBS setting.
PRBS Sets the number of the PRBS pattern stages for 32G
PPG/ED.
MCP/CP Set the standard test pattern for PCIe.
Insert Delay Symbol Sets whether to insert Delay Symbol in MCP/CP.
Cannot be set if the Specification Rev. setting is 3.0/3.1
(8.0 GT/s) or 4.0 (16.0 GT/s).
TS Option Opens the dialog box (Figure 4.4.2-2), where you can edit
specific PCIe link training sequence settings.