Analog Devices Blackfin ADSP-BF537, Hardware Reference Manual

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ADSP-BF537 Blackfin Processor Hardware Reference 20-25
Dynamic Power Management
All four registers are 16-bit MMRs and must be accessed with aligned
16-bit reads/writes. These registers are shown in
Figure 20-4 through
Figure 20-7 .
Table 20-11 shows the functions of the PLL/VR registers.
PLL_DIV Register
Table 20-11. PLL/VR Register Mapping
Register Name Function Notes
PLL_CTL PLL control regis-
ter Requires reprogramming sequence when writ-
ten
PLL_DIV PLL divisor register Can be written freely
PLL_STAT PLL status register Monitors active modes of operation
PLL_LOCKCNT PLL lock count
register Number of SCLKs allowed for PLL to relock
VR_CTL Voltage regulator
control register Requires PLL reprogramming sequence when
written
Figure 20-4. PLL Divide Register
PLL Divide Register (PLL_DIV)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1
0 - Reserved
1-15 - SCLK = VCO / X
CSEL[1:0] (Core Select)
0 0 0 0 0 0 0 0 0 0 0 0 1 0
00 - CCLK = VCO /1
01 - CCLK = VCO / 2
10 - CCLK = VCO / 4
11 - CCLK = VCO / 8
SSEL[3:0] (System Select)
Reset = 0x0005
0
0xFFC0 0004