Analog Devices Blackfin ADSP-BF537, Hardware Reference Manual

Page: 1061 / 1218

ADSP-BF537 Blackfin Processor Hardware Reference 20-15
Dynamic Power Management
and implements the changes made to the
PLL_CTL
register. After the
changes take effect, the processor operates with the new settings, including
the new operating mode, if one is programmed.
PLL Programming Sequence
If new values are assigned to
MSEL
or
DF
in the PLL control register
(
PLL_CTL
), the instruction sequence shown in Listing 20-1 and
Listing 20-2 puts those changes into effect. The PLL programming
sequence is also executed when transitioning between operating modes.
L
Changes to the divider-ratio bits,
CSEL
and
SSEL
, can be made
dynamically; they do not require execution of the PLL program-
ming sequence.
Listing 20-1. PLL Programming Sequence (ASM)
CLI R0 ; /* disable interrupts */
IDLE ; /* drain pipeline and send core into IDLE state */
STI R0 ; /* re-enable interrupts after wakeup */
The first two instructions in the sequence take the core to an idled state
with interrupts disabled; the interrupt mask (
IMASK
) is saved to the
R0
reg-
ister, and the instruction pipeline is halted. The PLL state machine then
loads the
PLL_CTL
register changes into the PLL. In order to break from
the idled state, the PLL wakeup event must be enabled in the system inter-
rupt controller interrupt wakeup register (set bit 0 of
SIC_IWR
).
Listing 20-2. PLL Programming Sequence (C)
#include <ccblkfn.h>
int temp;
temp = cli();
idle();
sti(temp);