Analog Devices Blackfin ADSP-BF537, Hardware Reference Manual

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ADSP-BF537 Blackfin Processor Hardware Reference 20-13
Dynamic Power Management
In addition to the mode transitions shown in Figure 20-2 , the PLL can be
modified while in active operating mode. Power to the PLL can be applied
and removed, and new clock-in to
VCO
clock (
CLKIN
to
VCO
) multiplier
ratios can be programmed. Described in detail below, these changes to the
PLL do not take effect immediately. As with operating mode transitions,
the PLL programming sequence must be executed for these changes to
take effect (see
“PLL Programming Sequence” on page 20-15 ).
• PLL disabled: In addition to being bypassed in the active mode, the
PLL can be disabled.
When the PLL is disabled, additional power savings are achieved
although they are relatively small. To disable the PLL, set the
PLL_OFF
bit in the
PLL_CTL
register, and then execute the PLL pro-
gramming sequence.
• PLL enabled: When the PLL is disabled, it can be re-enabled later
when additional performance is required.
The PLL must be re-enabled before transitioning to full on or sleep
operating modes. To re-enable the PLL, clear the
PLL_OFF
bit in
the
PLL_CTL
register, and then execute the PLL programming
sequence.
• New multiplier ratio in active mode: New clock-in to
VCO
clock
(
CLKIN
to
VCO
) multiplier ratios can be programmed while in active
mode.
Although the
CLKIN
to
VCO
multiplier changes are not realized in
active mode, forcing the PLL to lock to the new ratio in active
mode before transitioning to full on mode reduces the transition
time because the PLL is already locked to the new ratio. Note that
the PLL must be powered up to lock to the new ratio. To program
a new
CLKIN
to
VCO
multiplier, write the new
MSEL[5:0]
and/or
DF
values to the
PLL_CTL
register; then execute the PLL programming
sequence.