Analog Devices Blackfin ADSP-BF537, Hardware Reference Manual

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SDC Register Definitions
6-76 ADSP-BF537 Blackfin Processor Hardware Reference
The
EBUFE
bit in the
EBIU_SDGCTL
register enables this mode:
•
EBUFE = 0
Disable external buffering timing
•
EBUFE = 1
Enable external buffering timing
When
EBUFE = 1
, the SDRAM controller delays the data in write
accesses by one cycle, enabling external buffer registers to latch the
address and controls. In read accesses, the SDRAM controller sam-
ples data one cycle later to account for the one-cycle delay added by
the external buffer registers. When external buffering timing is
enabled, the latency of all accesses is increased by one cycle.
L
Connection of 4 x 4 bits rather than 1 x 16 bits increases the page
size by a factor of 4, thus resulting in fewer off page penalties.
• Fast back to back read to write (
FBBRW
)
The
FBBRW
bit enables an SDRAM read followed by write to occur
on consecutive cycles. In many systems, this is not possible because
the turn-off time of the SDRAM data pins is too long, leading to
bus contention with the succeeding write from the processor.
When this bit is 0, a clock cycle is inserted between read accesses
followed immediately by write accesses.
• Extended mode register enabled (
EMREN
)
The
EMREN
bit enables programming of the extended mode register
during startup. The extended mode register is used to control
SDRAM power consumption in certain mobile low power
SDRAMs. If the
EMREN
bit is enabled, then the
TCSR
and
PASR[1:0]
bits control the value written to the extended mode register.