Analog Devices Blackfin ADSP-BF537, Hardware Reference Manual

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Phase Locked Loop and Clock Control
20-6 ADSP-BF537 Blackfin Processor Hardware Reference
As long as the
MSEL
and
DF
control bits in the PLL control register
(
PLL_CTL
) remain constant, the PLL is locked.
L
If changing the clock ratio via writing a new
SSEL
value into
PLL_DIV
, take care that the enabled peripherals do not suffer data
loss due to
SCLK
frequency changes.
When changing clock frequencies in the PLL, the PLL requires time to
stabilize and lock to the new frequency. The PLL lock count register
(
PLL_LOCKCNT
) defines the number of
SCLK
cycles that occur before the
processor sets the
PLL_LOCKED
bit in the
PLL_STAT
register. When execut-
ing the PLL programming sequence, the internal PLL lock counter begins
incrementing upon execution of the
IDLE
instruction. The lock counter
increments by 1 each
SCLK
cycle. When the lock counter has incremented
to the value defined in the
PLL_LOCKCNT
register, the
PLL_LOCKED
bit is set.
Table 20-3. System Clock Ratio
Signal Name
SSEL[3:0] Divider Ratio
VCO/SCLK Example Frequency Ratios (MHz)
VCO
SCLK
0000 Reserved N/A N/A
0001 1:1 100 100
0010 2:1 200 100
0011 3:1 400 133
0100 4:1 500 125
0101 5:1 600 120
0110 6:1 600 100
N = 7–15 N:1 600 600/N