Analog Devices Blackfin ADSP-BF537, Hardware Reference Manual

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ADSP-BF537 Blackfin Processor Hardware Reference 2-11
Chip Bus Hierarchy
Arbitration of the External Bus
Arbitration for use of external port bus interface resources is required
because of possible contention between the potential masters of this bus. A
fixed-priority arbitration scheme is used. That is, core accesses via the
EAB will be of higher priority than those from the DMA external bus
(DEB).
DEB/EAB Performance
The DEB and the EAB support single word accesses of either 8-bit or
16-bit data types. The DEB and the EAB operate at the same frequency as
the PAB and the DAB, up to the maximum
SCLK
frequency specified in
the processor data sheet.
Memory DMA transfers can result in repeated accesses to the same mem-
ory location. Because the memory DMA controller has the potential of
simultaneously accessing on-chip and off-chip memory, considerable
throughput can be achieved. The throughput rate for an on-chip/off-chip
memory access is limited by the slower of the two accesses.
In the case where the transfer is from on-chip to on-chip memory or from
off-chip to off-chip memory, the burst accesses cannot occur simulta-
neously. The transfer rate is then determined by adding each transfer plus
an additional cycle between each transfer.
Table 2-2 shows many types of 16-bit memory DMA transfers. In the
table, it is assumed that no other DMA activity is conflicting with ongoing
operations. The numbers in the table are theoretical values. These values
may be higher when they are measured on actual hardware due to a variety
of reasons relating to the device that is connected to the EBIU.
For non-DMA accesses (for example, a core access via the EAB), a 32-bit
access to SDRAM (of the form
R0 = [P0];
where P0 points to an address
in SDRAM) is always more efficient than executing two 16-bit accesses (of