Analog Devices Blackfin ADSP-BF537, Hardware Reference Manual

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ADSP-BF537 Blackfin Processor Hardware Reference 6-65
External Bus Interface Unit
L
The minimum column width for a 256M byte SDRAM configura-
tion is 9 and the minimum column width for a 512M byte
SDRAM configuration is 10.
Using SDRAMs With Systems Smaller than 16M byte
It is possible to use SDRAMs smaller than 16M byte on the
ADSP-BF534, ADSP-BF536, and ADSP-BF537, as long as it is under-
stood how the resulting memory map is altered.
Figure 6-16 shows an
example where a 2M byte SDRAM (512K x 16 bits x 2 banks) is mapped
to the external memory interface. In this example, there are 11 row
addresses and 8 column addresses per bank. Referring to
Table 6-4 on
page 6-26 , the lowest available bank size (16M byte) for a device with 8
column addresses has 2 bank address lines (IA[23:22]) and 13 row address
lines (IA[21:9]). Therefore, 1 processor bank address line and 2 row
address lines are unused when hooking up to the SDRAM in the example.
This causes aliasing in the processor’s external memory map, which results
in the SDRAM being mapped into noncontiguous regions of the proces-
sor’s memory space.
32 8 .5 IA[24:23] IA[22:9] IA[8:1] IA[0]
16 11 4 IA[23:22] IA[21:12] IA[11:1] IA[0]
16 10 2 IA[23:22] IA[21:11] IA[10:1] IA[0]
16 9 1 IA[23:22] IA[21:10] IA[9:1] IA[0]
16 8 .5 IA[23:22] IA[21:9] IA[8:1] IA[0]
Table 6-13. Internal Address Mapping (Cont’d)
Ba
n
k
Si
ze
(Mb
yte)
EBSZ bits Col. A
ddr
.
Wi
d
th
(
C
A
W
)
EBCA
W bi
ts
Pa
ge
S
iz
e
(K B
yte)
Ba
n
k
A
ddr
ess
Ro
w
A
ddr
ess
Page
Column A
ddr
ess
By
te
A
ddr
ess