Analog Devices Blackfin ADSP-BF537, Hardware Reference Manual

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ADSP-BF537 Blackfin Processor Hardware Reference 1-9
Introduction
External Bus Interface Unit
The External Bus Interface Unit (EBIU) on the processor interfaces with a
wide variety of industry-standard memory devices. The controller consists
of an SDRAM controller and an asynchronous memory controller.
PC133 SDRAM Controller
The SDRAM controller provides an interface to a single bank of indus-
try-standard SDRAM devices or DIMMs. Fully compliant with the
PC133 SDRAM standard, the bank can be configured to contain between
16M and 512M bytes of memory.
A set of programmable timing parameters is available to configure the
SDRAM bank to support slower memory devices. The memory bank is
16 bits wide for minimum device count and lower system cost.
Asynchronous Controller
The asynchronous memory controller provides a configurable interface for
up to four separate banks of memory or I/O devices. Each bank can be
independently programmed with different timing parameters. This allows
connection to a wide variety of memory devices, including SRAM, ROM,
and flash EPROM, as well as I/O devices that interface with standard
memory control lines. Each bank occupies a 1M byte window in the pro-
cessor address space, but if not fully populated, these are not made
contiguous by the memory controller. The banks are 16 bits wide, for
interfacing to a range of memories and I/O devices.