Analog Devices Blackfin ADSP-BF537, Hardware Reference Manual

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Clock Signals
1-22 ADSP-BF537 Blackfin Processor Hardware Reference
If configured to generate a hardware reset, the watchdog timer resets both
the CPU and the peripherals. After a reset, software can determine if the
watchdog was the source of the hardware reset by interrogating a status bit
in the watchdog control register.
The timer is clocked by the system clock (
SCLK
), at a maximum frequency
of f
SCLK
.
Clock Signals
The processor can be clocked by an external crystal, a sine wave input, or a
buffered, shaped clock derived from an external clock oscillator.
This external clock connects to the processor’s
CLKIN
pin. The
CLKIN
input
cannot be halted, changed, or operated below the specified frequency dur-
ing normal operation. This clock signal should be a TTL-compatible
signal.
The core clock (
CCLK
) and system peripheral clock (
SCLK
) are derived from
the input clock (
CLKIN
) signal. An on-chip Phase Locked Loop (PLL) is
capable of multiplying the
CLKIN
signal by a user-programmable (1x to
63x) multiplication factor (bounded by specified minimum and maximum
VCO
frequencies). The default multiplier is 10x, but it can be modified by a
software instruction sequence. On-the-fly frequency changes can be made
by simply writing to the
PLL_DIV
register.
All on-chip peripherals are clocked by the system clock (
SCLK
). The system
clock frequency is programmable by means of the
SSEL[3:0]
bits of the
PLL_DIV
register.