Analog Devices Blackfin ADSP-BF537, Hardware Reference Manual

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Register Descriptions
11-46 ADSP-BF537 Blackfin Processor Hardware Reference
receive status (
RCVSTAT
) field in the
TWI_FIFO_STAT
register is updated. If
an access is performed while the FIFO buffer is empty, the data is
unknown and the FIFO buffer status remains indicating it is empty.
TWI_RCV_DATA16 Register
The TWI FIFO receive data double byte register (
TWI_RCV_DATA16
) holds
a 16-bit data value read from the FIFO buffer. To reduce interrupt output
rates and peripheral bus access times, a double byte receive data access can
be performed. Two data bytes can be read, effectively emptying the receive
FIFO buffer with a single access. The data is read in little endian byte
order as shown in
Figure 11-27 where byte 0 is the first byte received and
byte 1 is the second byte received. With each access, the receive status
(
RCVSTAT
) field in the
TWI_FIFO_STAT
register is updated to indicate it is
empty. If an access is performed while the FIFO buffer is not full, the read
data is unknown and the existing FIFO buffer data and its status remains
unchanged.
Figure 11-26. TWI FIFO Receive Data Single Byte Register
Figure 11-27. Little Endian Byte Order
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
TWI FIFO Receive Data Single Byte Register (TWI_RCV_DATA8)
All bits are RO.
RCVDATA8[7:0] (Receive
FIFO 8-Bit Data)
Reset = 0x0000 0xFFC0 1488
B1 B0
DATA IN REGISTER