Analog Devices Blackfin ADSP-BF537, Hardware Reference Manual

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Functional Description
5-42 ADSP-BF537 Blackfin Processor Hardware Reference
Figure 5-4 illustrates how an asynchronous FIFO could be connected. In
such a scenario the
REP
bit was cleared to let the
DMARx
request pin listen to
falling edges. The Blackfin processor does not evaluate the full flag such
FIFOs usually provide, because asynchronous polling of that signal would
reduce the system throughput drastically. Moreover, the processor first
fills the FIFO by initializing the
HMDMAx_ECINIT
register by the value 1024
which equals the depth of the FIFO. Once enabled, the MDMA automat-
ically transmits 1024 data words. Afterward it continues to transmit only
if the FIFO is emptied by its read strobe again. Most likely, the
HMDMAx_
BCINIT
register is programmed to be 1 in this case.
In the receive example shown in Figure 5-5 , the Blackfin processor again
does not use the FIFO’s internal control mechanism. Rather than testing
the empty flag, the processor counts the number of data words available in
the FIFO by its own
HMDMAx_ECOUNT
register. Theoretically, the MDMA
could immediately process data as soon as it is written into the FIFO by
the write strobe, but the fast MDMA engine would read out the FIFO
quickly and stall soon if the FIFO was not filled with new data promptly.
Streaming applications can balance the FIFO so that the producer is never
held off by a full FIFO and the consumer is never held by an empty FIFO.
This is accomplished by filling the FIFO half way and then letting both
consumer and producer run at the same speed. In this case the
HMDMAx_
ECINIT
register can be written with a negative value, which corresponds to
Figure 5-4. Transmit DMA Example Connection
WR
AMSx
1024K x 16 FIFO BLACKFIN
FF
D0 .. D15
DMARx
RD
I0 .. I15 O0 .. O15
AWE