Analog Devices Blackfin ADSP-BF537, Hardware Reference Manual

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PLL Registers
20-24 ADSP-BF537 Blackfin Processor Hardware Reference
To power down the internal supply:
1. If needed, ensure that the RTC, CAN, and/or PHY are enabled for
wakeup in the
SIC_IWR
register.
2. Write to
VR_CTL
, setting the
FREQ
bits to
b#00
, and the appropriate
wakeup bit to 1 (
CANWE
,
PHYWE
,
WAKE
on the ADSP-BF536 or
ADSP-BF537, and
CANWE
,
WAKE
on the ADSP-BF534). Optionally,
set the
CKELOW
bit if SDRAM data should be maintained.
3. Execute the PLL reprogramming sequence.
4. When the idle state is reached, V
DDINT
will transition to 0 V.
5. When the processor is woken up, whether by RTC, CAN, or PHY
on the ADSP-BF536 or ADSP-BF537, or by RTC or CAN on the
ADSP-BF534, or by a reset interrupt, the PLL relocks and the boot
sequence defined by the
BMODE[1:0]
pin settings takes effect.
a
Failure to allow V
DDINT
to complete the transition to 0 V before
waking up the processor can cause undesired results.
PLL Registers
The user interface to the PLL is through four memory-mapped registers
(MMRs):
• The PLL divide register (
PLL_DIV
)
• The PLL control register (
PLL_CTL
)
• The PLL status register (
PLL_STAT
)
• The PLL lock count register (
PLL_LOCKCNT
)