Analog Devices Blackfin ADSP-BF537, Hardware Reference Manual

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ADSP-BF537 Blackfin Processor Hardware Reference 12-63
SPORT Controllers
SPORTx_STAT Register
The SPORT status register (
SPORTx_STAT
) is used to determine if the
access to a SPORT RX or TX FIFO can be made by determining their full
or empty status. This register is shown in
Figure 12-33 .
The
TXF
bit in the SPORT status register indicates whether there is room
in the TX FIFO. The
RXNE
status bit indicates whether there are words in
the RX FIFO. The
TXHRE
bit indicates if the TX hold register is empty.
The transmit underflow status bit (
TUVF
) is set whenever the
TFS
signal
occurs (from either an external or internal source) while the TX shift regis-
ter is empty. The internally generated
TFS
may be suppressed whenever
SPORTx_TX
is empty by clearing the
DITFS
control bit in the SPORT con-
figuration register. The
TUVF
status bit is a sticky write-1-to-clear (W1C)
bit and is also cleared by disabling the SPORT (writing
TXEN = 0
).
For continuous transmission (
TFSR = 0
),
TUVF
is set at the end of a trans-
mitted word if no new word is available in the TX hold register.
The
TOVF
bit is set when a word is written to the TX FIFO when it is full.
It is a sticky W1C bit and is also cleared by writing
TXEN = 0
. Both
TXF
and
TOVF
are updated even when the SPORT is disabled.
When the SPORT RX hold register is full, and a new receive word is
received in the shift register, the receive overflow status bit (
ROVF
) is set in
the SPORT status register. It is a sticky W1C bit and is also cleared by
disabling the SPORT (writing
RXEN = 0
).
The
RUVF
bit is set when a read is attempted from the RX FIFO and it is
empty. It is a sticky W1C bit and is also cleared by writing
RXEN = 0
. The
RUVF
bit is updated even when the SPORT is disabled.