Analog Devices Blackfin ADSP-BF537, Hardware Reference Manual

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SDC Programming Model
6-56 ADSP-BF537 Blackfin Processor Hardware Reference
SDC Configuration
After a processor’s hardware or software reset, the SDC clocks are enabled;
however, the SDC must be configured and initialized. Before program-
ming the SDC and executing the powerup sequence, these steps are
required:
1. Ensure the clock to the SDRAM is stable after the power has stabi-
lized for the proper amount of time (typically 100
μ
s).
2. Write to the SDRAM refresh rate control register (
EBIU_SDRRC
).
3. Write to the SDRAM memory bank control register
(
EBIU_SDBCTL
).
4. Write to and SDRAM memory global control register
(
EBIU_SDGCTL
).
5. Perform SDRAM access.
The
SDRS
bit of the SDRAM control status register can be checked to
determine the current state of the SDC. If this bit is set, the SDRAM
powerup sequence has not been initiated.
The
RDIV
field of the
EBIU_SDRRC
register should be written to set the
SDRAM refresh rate.
The
EBIU_SDBCTL
register should be written to describe the sizes and
SDRAM memory configuration used (
EBSZ
and
EBCAW
) and to enable the
external bank (
EBE
). Note until the SDRAM powerup sequence has been
started, any access to SDRAM address space, regardless of the state of the
EBE
bit, generates an internal bus error, and the access does not occur
externally. For more information, see “Error Detection” on page 6-7.
The powerup latency can be estimated as:
t
RP
+ (8 x t
RFC
) + t
MRD
+ t
RCD