Analog Devices Blackfin ADSP-BF537, Hardware Reference Manual

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ADSP-BF537 Blackfin Processor Hardware Reference 20-3
Dynamic Power Management
Subject to the maximum
VCO
frequency, the PLL supports a wide range of
multiplier ratios and achieves multiplication of the input clock,
CLKIN
. To
achieve this wide multiplication range, the processor uses a combination
of programmable dividers in the PLL feedback circuit and output configu-
ration blocks.
Figure 20-1 illustrates a conceptual model of the PLL circuitry, configura-
tion inputs, and resulting outputs. In the figure, the
VCO
is an intermediate
clock from which the core clock (
CCLK
) and system clock (
SCLK
) are
derived.
PLL Clock Multiplier Ratios
The PLL control register (
PLL_CTL
) governs the operation of the PLL. For
details about the
PLL_CTL
register, see “PLL_CTL Register” on
page 20-26 .
The divide frequency (
DF
) bit and multiplier select (
MSEL[5:0]
) field con-
figure the various PLL clock dividers:
•
DF
enables the input divider
•
MSEL[5:0]
controls the feedback dividers
Figure 20-1. PLL Block Diagram
VCO
CLKIN
DF
MSEL[5:0]
SSEL[3:0]
DIVIDER
CCLK
SCLK
BYPASS
CSEL[1:0]
LOOP
FILTER
PHASE
DETECT
CLOCK
DIVIDE
AND
MUX
/1 or /2