Analog Devices Blackfin ADSP-BF537, Hardware Reference Manual

Page: 1072 / 1218

PLL Registers
20-26 ADSP-BF537 Blackfin Processor Hardware Reference
PLL_CTL Register
PLL_STAT Register
Figure 20-5. PLL Control Register
Figure 20-6. PLL Status Register
0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 1 0 1 0 0 0 0 0 0 0 0
See Table 20-1 on page 20-4
for CLKIN/VCO multiplication
factors
PLL Control Register (PLL_CTL)
BYPASS
0 - Do not bypass PLL
1 - Bypass PLL
MSEL[5:0]
(Multiplier Select)
DF (Divide Frequency)
0 - Pass CLKIN to PLL
1 - Pass CLKIN/2 to PLL
PLL_OFF
0 - Enable power to PLL
1 - Disable power to PLL
STOPCK (Stop Clock)
0 - CCLK on
1 - CCLK off
PDWN (Power Down)
0 - All internal clocks on
1 - All internal clocks off
Reset = 0x1400
0xFFC0 0000
Output Delay
0 - Do not add output delay
1 - Add approximately 200 ps
of delay to external memory
output signals
Input Delay
0 - Do not add input delay
1 - Add approximately 200 ps
of delay to the time when
inputs are latched on the
external memory interface
0 0 0 0 0 0 0 0
PLL Status Register (PLL_STAT)
Read only. Unless otherwise noted, 1 - Processor operating in this mode. For more infor-
mation, see “Operating Modes” on page 20-8.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 1 0 1 0 0 0 1
Reset = 0x00A2
ACTIVE_PLLENABLED
FULL_ON
ACTIVE_PLLDISABLED
PLL_LOCKED
0xFFC0 000C