Analog Devices Blackfin ADSP-BF537, Hardware Reference Manual

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EBIU Overview
6-6 ADSP-BF537 Blackfin Processor Hardware Reference
Registers
There are six control registers and one status register in the EBIU. They
are:
• Asynchronous memory global control register (
EBIU_AMGCTL
)
• Asynchronous memory bank control 0 register (
EBIU_AMBCTL0
)
• Asynchronous memory bank control 1 register (
EBIU_AMBCTL1
)
• SDRAM memory global control register (
EBIU_SDGCTL
)
• SDRAM memory bank control register (
EBIU_SDBCTL
)
• SDRAM refresh rate control register (
EBIU_SDRRC
)
• SDRAM control status register (
EBIU_SDSTAT
)
Each of these registers is described in detail in the AMC and SDC sections
later in this chapter.
Shared Pins
Both the AMC and the SDC share the external interface address and data
pins, as well as some of the control signals. These pins are shared:
•
ADDR[19:1]
, address bus
•
DATA[15:0]
, data bus
•
ABE[1:0]/SDQM[1:0]
, AMC byte enables/SDC data masks
•
BR, BG, BGH,
external bus access control signals
•
CLKOUT
, system clock for SDC and AMC
No other signals are multiplexed between the two controllers.