Analog Devices Blackfin ADSP-BF537, Hardware Reference Manual

Page: 1062 / 1218

Dynamic Power Management Controller
20-16 ADSP-BF537 Blackfin Processor Hardware Reference
This sequence behaves the same way as the ASM sequence in Listing 20-1 .
However, the interrupt mask (
IMASK
) is saved to the data element
temp
rather than to the
R0
register.
If the
PLL_CTL
register changes include a new
CLKIN
to
VCO
multiplier or
the changes reapply power to the PLL, the PLL needs to relock. To relock,
the PLL lock counter is first cleared, and then it begins incrementing,
once per
SCLK
cycle. After the PLL lock counter reaches the value pro-
grammed into the PLL lock count register (
PLL_LOCKCNT
), the PLL sets the
PLL_LOCKED
bit in the PLL status register (
PLL_STAT
), and the PLL asserts
the PLL wakeup interrupt.
Depending on how the
PLL_CTL
register is programmed, the processor
proceeds in one of the following four ways:
• If the
PLL_CTL
register is programmed to enter either active or full
on operating mode, the PLL generates a wakeup signal, and then
the processor continues with the
STI
instruction in the sequence, as
described in “PLL Programming Sequence” on page 20-15 .
When the state change enters full on mode from active mode or
active from full on, the PLL itself generates a wakeup signal that
can be used to exit the idled core state. The wakeup signal is gener-
ated by the PLL itself or another peripheral, watchdog or other
timer, RTC, or other source. For more information about events
that cause the processor to wakeup from being idled, see the “Pro-
gram Sequencer” chapter of the ADSP-BF53x/BF56x Blackfin
Processor Programming Reference.
• If the
PLL_CTL
register is programmed to enter the sleep operating
mode, the processor immediately transitions to the sleep mode and
waits for a wakeup signal before continuing.