Analog Devices Blackfin ADSP-BF537, Hardware Reference Manual

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ADSP-BF537 Blackfin Processor Hardware Reference 11-39
Two Wire Interface Controller
Additional information for the
TWI_FIFO_CTL
register bits includes:
• Receive buffer interrupt length (
RCVINTLEN
)
This bit determines the rate at which receive buffer interrupts are
to be generated. Interrupts may be generated with each byte
received or after two bytes are received.
[1] An interrupt (
RCVSERV
) is set when the
RCVSTAT
field in the
TWI_FIFO_STAT
register indicates two bytes in the FIFO are full
(11).
[0] An interrupt (
RCVSERV
) is set when
RCVSTAT
indicates one or
two bytes in the FIFO are full (01 or 11).
• Transmit buffer interrupt length (
XMTINTLEN
)
This bit determines the rate at which transmit buffer interrupts are
to be generated. Interrupts may be generated with each byte trans-
mitted or after two bytes are transmitted.
[1] An interrupt (
XMTSERV
) is set when the
XMTSTAT
field in the
TWI_FIFO_STAT
register indicates two bytes in the FIFO are empty
(00).
[0] An interrupt (
XMTSERV
) is set when
XMTSTAT
indicates one or
two bytes in the FIFO are empty (01 or 00).
• Receive buffer flush (
RCVFLUSH
)
[1] Flush the contents of the receive buffer and update the
RCVSTAT
status bit to indicate the buffer is empty. This state is held until
this bit is cleared. During an active receive the receive buffer in this
state responds to the receive logic as if it is full.
[0] Normal operation of the receive buffer and its status bits.