MC96F6432
76
June 22, 2018 Ver. 2.9
9.4 P1 Port
9.4.1 P1 Port Description
P1 is 8-bit I/O port. P1 control registers consist of P1 data register (P1), P1 direction register (P1IO), debounce
enable register (P15DB), P1 pull-up resistor selection register (P1PU), and P1 open-drain selection register
(P1OD) . Refer to the port function selection registers for the P1 function selection.
9.4.2 Register description for P1
P1 (P1 Data Register) : 88H
7
6
5
4
3
2
1
0
P17
P16
P15
P14
P13
P12
P11
P10
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value : 00H
P1[7:0]
I/O Data
Note) Do not use the
“direct bit test and branch” instruction for input port, more detail information is at
Appendix B.
Example) Avoid direct input port bit test and branch condition as below
If(P10)
→
if(P1 & 0x01)
P1IO (P1 Direction Register) : B1H
7
6
5
4
3
2
1
0
P17IO
P16IO
P15IO
P14IO
P13IO
P12IO
P11IO
P10IO
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value : 00H
P1IO[7:0]
P1 Data I/O Direction
0
Input
1
Output
NOTE: EINT6/ENINT7/EINT11/EINT12/SS2/EC1 function possible
when input
P1PU (P1 Pull-up Resistor Selection Register) : ADH
7
6
5
4
3
2
1
0
P17PU
P16PU
P15PU
P14PU
P13PU
P12PU
P11PU
P10PU
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value : 00H
P1PU[7:0]
Configure Pull-up Resistor of P1 Port
0
Disable
1
Enable
Summary of Contents for MC96F6432 Series
Page 24: ...MC96F6432 24 June 22 2018 Ver 2 9 4 Package Diagram Figure 4 1 48 Pin LQFP 0707 Package...
Page 25: ...MC96F6432 June 22 2018 Ver 2 9 25 Figure 4 2 44 Pin MQFP Package...
Page 26: ...MC96F6432 26 June 22 2018 Ver 2 9 Figure 4 3 32 Pin LQFP Package...
Page 27: ...MC96F6432 June 22 2018 Ver 2 9 27 Figure 4 4 32 Pin SOP Package...
Page 28: ...MC96F6432 28 June 22 2018 Ver 2 9 Figure 4 5 28 Pin SOP Package...