Abov MC96F6432 Series, User Manual

Page: 154 / 327

MC96F6432
154 June 22, 2018 Ver. 2.9
11.8.3 16-Bit Timer/Counter 3 Mode
The 16-bit timer/counter mode is selected by control register as shown in Figure 11.31.
The 16-bit timer have counter and data register. The counter register is increased by internal or external clock
input. Timer 3 can use the input clock with one of 2, 4, 8, 32, 128, 512 and 2048 prescaler division rates
(T3CK[2:0]).
A 16-bit timer/counter register T3CNT, T4CNT are incremented from 0000H to FFFFH until it matches T3DR,
T4DR and then cleared to 0000H. The match signal output generates the Timer 3 Interrupt (No timer 4 interrupt).
The clock source is selected from T3CK[2:0] and 16BIT bit must be set to
‘1’. Timer 3 is LSB 8-bit, the timer 4 is
MSB 8-bit.
The external clock (EC3) counts up the timer at the rising edge. If the EC3 is selected as a clock source by
T3CK[2:0], EC3 port should be set to the input port by P00IO bit.
P
r
e
s
c
a
l
e
r
fx
M
U
X
fx/2
T4CNT/T3CNT (16Bit)
EC3
fx/4
fx/8
fx/32
fx/128
fx/512
fx/2048
3
T3CK[2:0]
T3CN
16-bit Timer 3 Counter
T4DR/T3DR (16Bit)
Comparator
T3IFR
To interrupt
block
T3O
16-bit Timer 3 Data Register
INT_ACK
Clear
Clear
Match
T3ST
MSB LSB
MSB LSB
T3EN
T3CR
1
ADDRESS:1000H (ESFR)
INITIAL VALUE : 0000_0000B
–
T3MS T3CK2 T3CK1 T3CK0 T3CN T3ST
–
0 X
X X X
X
16BIT
T4CR
1
ADDRESS:1002H (ESFR)
INITIAL VALUE : 0000_0000B
T4MS T4CN T4ST T4CK3 T4CK2 T4CK1 T4CK0
0 X
X 1 1
1
1
NOTE) The T4CR.7 bit (16BIT) should be set to
‘1’ and the T4CK[3:0] should be set to “1111b”.
Figure 11.31 16-Bit Timer/Counter Mode for Timer 3