Abov MC96F6432 Series, User Manual

Page: 111 / 327

MC96F6432
June 22, 2018 Ver. 2.9 111
11.1.3 Register Map
Table 11-1 Clock Generator Register Map
Name Address Dir Default Description
SCCR 8AH R/W 00H System and Clock Control Register
OSCCR C8H R/W 20H Oscillator Control Register
11.1.4 Clock Generator Register Description
The clock generator register uses clock control for system operation. The clock generation consists of System
and clock control register and oscillator control register.
11.1.5 Register Description for Clock Generator
SCCR (System and Clock Control Register) : 8AH
7 6 5 4 3 2 1 0
– – – – – –
SCLK1 SCLK0
– – – – – –
R/W R/W
Initial value : 00H
SCLK [1:0] System Clock Selection Bit
SCLK1 SCLK0 Description
0 0 INT RC OSC (f
IRC
) for system clock
0 1 External Main OSC (f
XIN
) for system clock
1 0 External Sub OSC (f
SUB
) for system clock
1 1 Not used