Abov MC96F6432 Series, User Manual

Page: 235 / 327

MC96F6432
June 22, 2018 Ver. 2.9 235
11.13.4 USI1 Clock Generation
Figure 11.79 Clock Generation Block Diagram (USI1)
The clock generation logic generates the base clock for the transmitter and receiver. The USI1 supports four
modes of clock operation and those are normal asynchronous, double speed asynchronous, master synchronous
and slave synchronous mode. The clock generation scheme for master SPI and slave SPI mode is the same as
master synchronous and slave synchronous operation mode. The USI1MS[1:0] bits in USI1CR1 register selects
asynchronous or synchronous operation. Asynchronous double speed mode is controlled by the DBLS1 bit in the
USI1CR2 register. The MASTER1 bit in USI1CR3 register controls whether the clock source is internal (master
mode, output pin) or external (slave mode, input pin). The SCK1 pin is active only when the USI1 operates in
synchronous or SPI mode.
Following table shows the equations for calculating the baud rate (in bps).
Table 11-22 Equations for Calculating USI1 Baud Rate Register Setting
Operating Mode Equation for Calculating Baud Rate
Asynchronous Normal Mode (DBLS1=0)
Baud Rate =
fx
16( 1)
Asynchronous Double Speed Mode (DBLS1=1)
Baud Rate =
fx
8( 1)
Synchronous or SPI Master Mode
Baud Rate =
fx
2( 1)
SCK1
Prescaling
Up-Counter
USI1BD
/2 /8
Sync Register
M
U
X
M
U
X
M
U
X
M
U
X
/2
Edge
Detector
SCLK
f
SCLK
(1)
txclk
rxclk
USI1MS[1:0]
DBLS1
MASTER1
CPOL1