Abov MC96F6432 Series, User Manual

Page: 63 / 327

MC96F6432
June 22, 2018 Ver. 2.9 63
8.4 SFR Map
8.4.1 SFR Map Summary
Table 8-1 SFR Map Summary
00H/8H
(1)
01H/9H 02H/0AH 03H/0BH 04H/0CH 05H/0DH 06H/0EH 07H/0FH
0F8H IP1
–
FSADRH FSADRM FSADRL FIDR FMCR P5FSR
0F0H
B
USI1ST1 USI1ST2 USI1BD USI1SDHR USI1DR USI1SCLR USI1SCHR
0E8H RSTFR USI1CR1 USI1CR2 USI1CR3 USI1CR4 USI1SAR P3FSR P4FSR
0E0H ACC USI0ST1 USI0ST2 USI0BD USI0SDHR USI0DR USI0SCLR USI0SCHR
0D8H LVRCR USI0CR1 USI0CR2 USI0CR3 USI0CR4 USI0SAR P0DB P15DB
0D0H PSW P5IO P0FSRL P0FSRH P1FSRL P1FSRH P2FSRL P2FSRH
0C8H OSCCR P4IO
– – – – – –
0C0H EIFLAG0 P3IO T2CRL T2CRH T2ADRL T2ADRH T2BDRL T2BDRH
0B8H IP P2IO T1CRL T1CRH T1ADRL T1ADRH T1BDRL T1BDRH
0B0H P5 P1IO T0CR T0CNT
T0DR/
T0CDR
SPICR SPIDR SPISR
0A8H IE IE1 IE2 IE3 P0PU P1PU P2PU P3PU
0A0H P4 P0IO EO P4PU EIPOL0L EIPOL0H EIFLAG1 EIPOL1
98H P3 LCDCRL LCDCRH LCDCCR ADCCRH ADCCRH ADCDRL ADCDRH
90H P2 P0OD P1OD P2OD P4OD P5PU WTCR BUZCR
88H P1
WTDR/
WTCNT
SCCR BITCR BITCNT WDTCR
WDTDR/
WDTCNT
BUZDR
80H P0 SP DPL DPH DPL1 DPH1 LVICR PCON
NOTE) 1. 00H/8H(1), These registers are bit-addressable.
2. Do not use the
“direct bit test and branch” instruction on P0, P1, P2, P3, P4, P5 and EIFLAG0
registers.
More detail information is at Appendix B.
Example) Avoid direct input port bit test and branch condition as below
If(P00)
→
if(P0 & 0x01)
-
Reserved
M8051 compatible