Abov MC96F6432 Series, User Manual

Page: 211 / 327

MC96F6432
June 22, 2018 Ver. 2.9 211
11.12.16 USI0 I2C Start / Repeated Start / Stop
One master can issue a START (S) condition to notice other devices connected to the SCL0, SDA0 lines that it
will use the bus. A STOP (P) condition is generated by the master to release the bus lines so that other devices
can use it.
A high to low transition on the SDA0 line while SCL0 is high defines a START (S) condition.
A low to high transition on the SDA0 line while SCL0 is high defines a STOP (P) condition.
START and STOP conditions are always generated by the master. The bus is considered to be busy after
START condition. The bus is considered to be free again after STOP condition, ie, the bus is busy between
START and STOP condition. If a repeated START condition (Sr) is generated instead of STOP condition, the bus
stays busy. So, the START and repeated START conditions are functionally identical.
Figure 11.68 START and STOP Condition (USI0)
11.12.17 USI0 I2C Data Transfer
Every byte put on the SDA0 line must be 8-bits long. The number of bytes that can be transmitted per transfer
is unlimited. Each byte has to be followed by an acknowledge bit. Data is transferred with the most significant bit
(MSB) first. If a slave can
’t receive or transmit another complete byte of data until it has performed some other
function, it can hold the clock line SCL0 LOW to force the master into a wait state. Data transfer then continues
when the slave is ready for another byte of data and releases clock line SCL0.
Figure 11.69 Data Transfer on the I2C-Bus (USI0)
START or Repeated
START Condition
S
or
Sr
STOP or Repeated
START Condition
Sr
or
P
MSB
Acknowledgement
Signal form Slave
Acknowledgement
Signal form Slave
Byte Complete,
Interrupt within Device
Clock line held low while
interrupts are served.
1 9 1 9
ACK ACK
SDA0
SCL0
Sr
P
SCL0
SDA0
START Condition
S P
STOP Condition