MC96F6432
June 22, 2018 Ver. 2.9
307
FMCR (Flash Mode Control Register) : FEH
7
6
5
4
3
2
1
0
FMBUSY
–
–
–
–
FMCR2
FMCR1
FMCR0
R
–
–
–
–
R/W
R/W
R/W
Initial value : 00H
FMBUSY
Flash Mode Busy Bit. This bit will be used for only debugger.
0
No effect when
“1” is written
1
Busy
FMCR[2:0]
Flash Mode Control Bits. During a flash mode operation, the CPU is
hold and the global interrupt is on disable state regardless of the IE.7
(EA) bit.
FMCR2
FMCR1
FMCR0
Description
0
0
1
Select flash page buffer reset mode
and start regardless of the FIDR
value (Clear all 64bytes to
‘0’)
0
1
0
Select flash sector erase mode and
start operation when the
FIDR=
”10100101b’
0
1
1
Select flash sector write mode and
start operation when the
FIDR=
”10100101b’
1
0
0
Select flash sector Code Write
Protection and start operation when
the FIDR=
”10100101b’
Others Values: No operation
(These bits are automatically cleared to logic
‘00H’ immediately after
one time operation)
Summary of Contents for MC96F6432 Series
Page 24: ...MC96F6432 24 June 22 2018 Ver 2 9 4 Package Diagram Figure 4 1 48 Pin LQFP 0707 Package...
Page 25: ...MC96F6432 June 22 2018 Ver 2 9 25 Figure 4 2 44 Pin MQFP Package...
Page 26: ...MC96F6432 26 June 22 2018 Ver 2 9 Figure 4 3 32 Pin LQFP Package...
Page 27: ...MC96F6432 June 22 2018 Ver 2 9 27 Figure 4 4 32 Pin SOP Package...
Page 28: ...MC96F6432 28 June 22 2018 Ver 2 9 Figure 4 5 28 Pin SOP Package...
