Abov MC96F6432 Series, User Manual

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MC96F6432
266 June 22, 2018 Ver. 2.9
USI1CR4 (USI1 Control Register 4: For I2C mode) : ECH
7 6 5 4 3 2 1 0
IIC1IFR
–
TXDLYENB1 IIC1IE ACK1EN IMASTER1 STOPC1 STARTC1
R
–
R/W R/W R/W R R/W R/W
Initial value : 00H
IIC1IFR This is an interrupt flag bit for I2C mode. When an interrupt occurs, this
bit becomes
‘1’. This bit is cleared when all interrupt source bits in the
USI1ST2 register are cleared to
“0b”. Writing “1” has no effect.
0 I2C interrupt no generation
1 I2C interrupt generation
TXDLYENB1 USI1SDHR register control bit
0 Enable USI1SDHR register
1 Disable USI1SDHR register
IIC1IE Interrupt Enable bit for I2C mode
0 Interrupt from I2C is inhibited (use polling)
1 Enable interrupt for I2C
ACK1EN Controls ACK signal Generation at ninth SCL1 period.
0 No ACK signal is generated (SDA1 =1)
1 ACK signal is generated (SDA1 =0)
NOTES) ACK signal is output (SDA1 =0) for the following 3 cases.
1. When received address packet equals to USI1SLA bits in USI1SAR.
2. When received address packet equals to value 0x00 with GCALL1
enabled.
3. When I2C operates as a receiver (master or slave)
IMASTER1 Represent operating mode of I2C
0 I2C is in slave mode
1 I2C is in master mode
STOPC1
When I2C is master, STOP condition generation
0 No effect
1 STOP condition is to be generated
STARTC1 When I2C is master, START condition generation
0 No effect
1 START or repeated START condition is to be generated