Abov MC96F6432 Series, User Manual

Page: 231 / 327

MC96F6432
June 22, 2018 Ver. 2.9 231
USI0ST2 (USI0 Status Register 2: For I2C mode) : E2H
7 6 5 4 3 2 1 0
GCALL0 TEND0 STOPD0 SSEL0 MLOST0 BUSY0 TMODE0 RXACK0
R/W R/W R/W R/W R/W R/W R R/W
Initial value : 00H
GCALL0
(NOTE)
This bit has different meaning depending on whether I2C is master or
slave. When I2C is a master, this bit represents whether it received
AACK (address ACK) from slave.
0 No AACK is received (Master mode)
1 AACK is received (Master mode)
When I2C is a slave, this bit is used to indicated general call.
0 General call address is not detected (Slave mode)
1 General call address is detected (Slave mode)
TEND0
(NOTE)
This bit is set when 1-byte of data is transferred completely
0 1 byte of data is not completely transferred
1 1 byte of data is completely transferred
STOPD0
(NOTE)
This bit is set when a STOP condition is detected.
0 No STOP condition is detected
1 STOP condition is detected
SSEL0
(NOTE)
This bit is set when I2C is addressed by other master.
0 I2C is not selected as a slave
1 I2C is addressed by other master and acts as a slave
MLOST0
(NOTE)
This bit represents the result of bus arbitration in master mode.
0 I2C maintains bus mastership
1 I2C maintains bus mastership during arbitration process
BUSY0
This bit reflects bus status.
0 I2C bus is idle, so a master can issue a START condition
1 I2C bus is busy
TMODE0 This bit is used to indicate whether I2C is transmitter or receiver.
0 I2C is a receiver
1 I2C is a transmitter
RXACK0 This bit shows the state of ACK signal
0 No ACK is received
1 ACK is received at ninth SCL period
NOTE)
1. The GCALL0, TEND0, STOPD0, SSEL0, and MLOST0 bits can be source
of interrupt.
2. When an I2C interrupt occurs except for STOP mode, the SCL0 line is hold
LOW. To release SCL0, Clear to
“0b” all interrupt source bits in USI0ST2
register.
3. The GCALL0, TEND0, STOPD0, SSEL0, MLOST0, and RXACK0 bits are
cleared when
“0b” is written to the corresponding bit.