MC96F6432
June 22, 2018 Ver. 2.9
295
LVRCR (Low Voltage Reset Control Register) : D8H
7
6
5
4
3
2
1
0
LVRST
–
–
LVRVS3
LVRVS2
LVRVS1
LVRVS0
LVREN
R/W
–
–
R/W
R/W
R/W
R/W
R/W
Initial value : 00H
LVRST
LVR Enable when Stop Release
0
Not effect at stop release
1
LVR enable at stop release
NOTES)
When this bit is
‘1’, the LVREN bit is cleared to ‘0’ by stop mode to
release. (LVR enable)
When this bit is
‘0’, the LVREN bit is not effect by stop mode to
release.
LVRVS[3:0]
LVR Voltage Select
LVRVS3 LVRVS2 LVRVS1 LVRVS0 Description
0
0
0
0
1.60V
0
0
0
1
2.00V
0
0
1
0
2.10V
0
0
1
1
2.20V
0
1
0
0
2.32V
0
1
0
1
2.44V
0
1
1
0
2.59V
0
1
1
1
2.75V
1
0
0
0
2.93V
1
0
0
1
3.14V
1
0
1
0
3.38V
1
0
1
1
3.67V
1
1
0
0
4.00V
1
1
0
1
4.40V
1
1
1
0
Not available
1
1
1
1
Not available
LVREN
LVR Operation
0
LVR Enable
1
LVR Disable
NOTES) 1. The LVRST, LVRVS[3:0] bits are cleared by a power-on reset but are retained by other reset signals.
2. The LVRVS[3:0] bits should be set to ‘0000b’ while LVREN bit is “1”.
Summary of Contents for MC96F6432 Series
Page 24: ...MC96F6432 24 June 22 2018 Ver 2 9 4 Package Diagram Figure 4 1 48 Pin LQFP 0707 Package...
Page 25: ...MC96F6432 June 22 2018 Ver 2 9 25 Figure 4 2 44 Pin MQFP Package...
Page 26: ...MC96F6432 26 June 22 2018 Ver 2 9 Figure 4 3 32 Pin LQFP Package...
Page 27: ...MC96F6432 June 22 2018 Ver 2 9 27 Figure 4 4 32 Pin SOP Package...
Page 28: ...MC96F6432 28 June 22 2018 Ver 2 9 Figure 4 5 28 Pin SOP Package...
