3152B User Manual
Publication No. 980935 Rev. A
3-24
Operation
EADS North America Test and Services
throughout the entire range, but if you increase the number of
points by two, then the 3152B will generate an error.
Note that for compatibility with older code that was used with
Model 3152A, you may select the Legacy Format mode, where the
limits for the sample clock change to 100 MS/s, but the waveform
size can be an integer multiple of two.
Using the
External Sample
Clock Input
The internal sample clock generator has a wide dynamic range that
allows the creation of an infinite number of waveforms and
frequencies. With its top frequency reaching frequencies close to
300 MHz, it must use dividers to create lower frequencies. Such
dividers can increase phase noise and jitter. Some applications
require better stability and phase noise, making a single-tone
sample clock source the most desired source.
The 3152B does not have a single-tone sample clock source, but it
provides a front-panel input, SCLK IN, that can accept a clock from
an external source. When this input is in use, the internal clock
generator is disabled, and the 3152B waveforms are clocked at a
rate defined by the external signal. Using an external clock source
can improve phase noise and jitter to approximately 20 dB/Hz at
10 kHz offset from the carrier.
Apply the external sample clock signal to the front panel SCLK IN
connector. Make sure your signal level is within the levels specified
in Appendix A. The following commands select the source of the
sample clock input:
freq:rast:sour int
This is the default selection, where the
3152B self-generates its sample clock signal.
All other inputs are disabled.
freq:rast:sour ext
This selects the front panel SCLK
IN
connector as the source of the sample clock
signal. Observe the signal range and levels
as specified in Appendix A.
freq:rast:sour eclt0
This selects the backplane ECLTrg0 line as
the sample clock source. This is a special
mode that allows synchronization between
adjacent 3152B modules. Note that the VXI
specifications limit the ECLTrg0 frequency to
62.5
MHz. Backplane synchronization is
covered in a separate section.
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