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SYNC_SEG
PRSEG
PHSEG1
PHSEG2
Time segment 2
(TSEG2)
Time segment 1 (TSEG1)
1-bit time (8–25 time quanta)
2–16 time quanta
1 time quanta
Figure 15.8 Detailed Description of One Bit
SYNC_SEG is a segment for establishing the synchronization of nodes on the CAN bus. Normal
bit edge transitions occur in this segment. PRSEG is a segment for compensating for the physical
delay between networks. PHSEG1 is a buffer segment for correcting phase drift (positive). This
segment is extended when synchronization (resynchronization) is established. PHSEG2 is a buffer
segment for correcting phase drift (negative). This segment is shortened when synchronization
(resynchronization) is established. Limits on the settable value (TSEG1, TSEG2, BRP, sample
point, and SJW) are shown in table 15.2.
Table 15.2 Limits for the Settable Value
Name
Abbreviation
Min. Value
Max. Value
Time segment 1
TSEG1
B
′
0011
*
2
B
′
1111
Time segment 2
TSEG2
B
′
001
*
3
B
′
111
Baud rate prescaler
BRP
B
′
000000 B
′
111111
Bit sample point
BSP
B
′
0 B
′
1
Re-synchronization jump width
SJW
*
1
B
′
00 B
′
11
Notes: 1. SJW is stipulated in the CAN specifications:
3
≥
SJW
≥
0
2. The minimum value of TSEG2 is stipulated in the CAN specifications:
TSEG2
≥
SJW
3. The minimum value of TSEG1 is stipulated in the CAN specifications:
TSEG1 > TSEG2
Содержание H8S/2627
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