Rev. 1.0, 09/02, page 372 of 568
Bit
Bit Name
Initial Value
R/W
Description
8 IRR0
1
R/(W)
*
Reset Interrupt Flag
Status flag indicating that the HCAN module has
been reset. This bit cannot be masked by the
interrupt mask register (IMR). If this bit is not
cleared to 0 after entering power-on reset or
returning from software standby mode, interrupt
processing will start immediately when the interrupt
controller enables interrupts.
[Setting condition]
•
When the reset operation has finished after
entering power-on reset or software standby
mode
[Clearing condition]
•
Writing
1
7 to
5
All
0
Reserved
These bits are always read as 0. The write value
should always be 0.
4 IRR12
0
R/(W)
*
Bus Operation Interrupt Flag
Status flag indicating detection of a dominant bit
due to bus operation when the HCAN module is in
HCAN sleep mode.
[Setting condition]
•
Bus operation (dominant bit) detection in HCAN
sleep mode
[Clearing condition]
•
Writing
1
3, 2
All
0
Reserved
These bits are always read as 0. The write value
should always be 0.
Содержание H8S/2627
Страница 22: ...Rev 1 0 09 02 page xx of xxxvi Index 565 ...
Страница 30: ...Rev 1 0 09 02 page xxviii of xxxiv ...
Страница 36: ...Rev 1 0 09 02 page xxxiv of xxxiv Table 23 9 Flash Memory Characteristics 561 ...
Страница 82: ...Rev 1 0 09 02 page 46 of 568 ...
Страница 88: ...Rev 1 0 09 02 page 52 of 568 ...
Страница 98: ...Rev 1 0 09 02 page 62 of 568 ...
Страница 156: ...Rev 1 0 09 02 page 120 of 568 ...
Страница 390: ...Rev 1 0 09 02 page 354 of 568 ...
Страница 480: ...Rev 1 0 09 02 page 444 of 568 ...
Страница 512: ...Rev 1 0 09 02 page 476 of 568 ...
Страница 527: ...Rev 1 0 09 02 page 491 of 568 21 8 5 Writing to MSTPCR MSTPCR should only be written to by the CPU ...
Страница 528: ...Rev 1 0 09 02 page 492 of 568 ...
Страница 580: ...Rev 1 0 09 02 page 544 of 568 ...