Rev. 1.0, 09/02, page 66 of 568
5.3.1
Interrupt Priority Registers A to M (IPRA to IPRM)
The IPR registers are thirteen 8-bit readable/writable registers that set priorities (levels 7 to 0) for
interrupts other than NMI.
The correspondence between interrupt sources and IPR settings is shown in table 5.2. Setting a
value in the range from H
′
0 to H
′
7 in the 3-bit groups of bits 0 to 2 and 4 to 6 sets the priority of
the corresponding interrupt.
Bit
Bit Name
Initial Value
R/W
Description
7
0
Reserved
These bits are always read as 0.
6
5
4
IPR6
IPR5
IPR4
1
1
1
R/W
R/W
R/W
Sets the priority of the corresponding interrupt
source.
000: Priority level 0 (Lowest)
001: Priority level 1
010: Priority level 2
011: Priority level 3
100: Priority level 4
101: Priority level 5
110: Priority level 6
111: Priority level 7 (Highest)
3
0
Reserved
These bits are always read as 0.
2
1
0
IPR2
IPR1
IPR0
1
1
1
R/W
R/W
R/W
Sets the priority of the corresponding interrupt
source.
000: Priority level 0 (Lowest)
001: Priority level 1
010: Priority level 2
011: Priority level 3
100: Priority level 4
101: Priority level 5
110: Priority level 6
111: Priority level 7 (Highest)
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