Rev. 1.0, 09/02, page 251 of 568
Bit
Bit Name
Initial
Value
R/W
Description
4
0 R/W
Reserved
This bit is a readable/writable bit, but the write value
should always be 0.
3
2
OS3
OS2
0
0
R/W
R/W
Output Select 3 and 2
These bits specify how the timer output level is to be
changed by a compare-match B of TCORB and
TCNT.
00: No change when compare-match B occurs
01: 0 is output when compare-match B occurs
10: 1 is output when compare-match B occurs
11: Output is inverted when compare-match B occurs
(toggle output)
1
0
OS1
OS0
0
0
R/W
R/W
Output Select 1 and 0
These bits specify how the timer output level is to be
changed by a compare-match A of TCORA and
TCNT.
00: No change when compare-match A occurs
01: 0 is output when compare-match A occurs
10: 1 is output when compare-match A occurs
11: Output is inverted when compare-match A occurs
(toggle output)
Note:
*
Only a 0 can be written to this bit, to clear the flag.
11.4 Operation
11.4.1 Pulse
Output
Figure 11.2 shows an example of arbitrary duty cycle pulse output.
1.
Set TCR in CCR1 to 0 and CCLR0 to 1 to clear TCNT by a TCORA compare-match.
2.
Set OS3 to OS0 bits in TCSR to B
′
0110 to output 1 by a compare-match A and 0 by compare-
match B.
By the above settings, waveforms with the cycle of TCORA and the pulse width of TCRB can be
output without software intervention.
Содержание H8S/2627
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